1. Field of the Invention
The present invention relates to a semiconductor memory device including a global IO line with a low-amplitude driving voltage signal applied thereto, and more particularly to a semiconductor memory device including a global IO line with a low-amplitude driving voltage signal applied thereto, which reduces the amplitude of a driving voltage signal applied to the global IO line, thereby decreasing power consumption for data transmission and also overcoming problems occurring in a high speed operation due to the use of high-amplitude voltage signals, thereby allowing a high frequency operation.
2. Description of the Related Art
DRAM (Dynamic Random Access Memory) is a type of volatile memory including cells, each of which is composed of a transistor and a capacitor to store data. Data input/output operations as basic functions of a DRAM cell are carried out by turning on/off a word line serving as a gate input to a transistor in the DRAM cell.
FIG. 1 is a block diagram showing the internal configuration of a general DRAM device for inputting and outputting data. As shown in FIG. 1, a memory cell region in the general DRAM device is divided into a plurality of banks. Data stored in each cell is read by transferring the cell data amplified by an IO (Input/Output) sense amplifier to a DQ block via a global IO line. External input data is written to a memory cell by transferring the external data input through a DQ block to a write driver via a global IO line and then storing the transferred data in the memory cell.
As demand for high speed operation of the DRAM device increases, the need to stabilize the high speed operation of each element in the DRAM device even in high frequency environments increases, and, in particular, the need to decrease power consumption for reading and writing data via a global IO line and also to prevent a decrease in a timing margin during the high speed operation via the global IO line arises.
However, in the prior art, voltage signals of the same voltage level as an internal voltage Vint used as Vperi or Vdd are used to input and output data via the global IO lines. When data input/output operations are performed in the general DRAM input/output configuration, the use of high amplitude signals for data transmission via the global IO lines causes an increase in power consumption and ground bouncing. In addition, different lengths of transmission lines between banks and DQ blocks cause data input and output to and from the banks to have different flight times and also reduces the timing margin for latching data, thereby causing problems in the high speed operation.